module dds_top(
//global
input wire i_clk,//50M
input wire i_rst,
//spi
input wire i_spi_sclk,
input wire i_spi_miso,
input wire i_spi_nss,
//dac
output wire o_dac_clk,
output wire [15:0]o_dac_data
);
wire clk;//main clk,150M
wire mmcm_locked;
wire asy_rst_wire;
reg [7:0]asy_rst_reg;
wire asy_rst;
reg [7:0]spi_sclk_reg;
reg [7:0]spi_miso_reg;
reg [7:0]spi_nss_reg;
wire spi_sclk_pos;
wire spi_nss_neg;
wire spi_nss_pos;
reg [14:0]spi_addr;
reg [15:0]spi_data;
reg [7:0]spi_cnt;
reg [31:0]spi_miso_data;
reg [15:0]spi_cnt_reg;
reg spi_wen;
reg [11:0]phase;//phase: 0-4095
///////////////////clk and reset///////////////////
clk_wiz u_clk_wiz
(
// Clock in ports
.clk_in1 ( i_clk ),//50M
// Clock out ports
.clk_out1 ( clk ), //150M
// Status and control signals
.reset ( i_rst ),
.locked ( mmcm_locked )
);
assign asy_rst_wire = i_rst | (~mmcm_locked);
always@(posedge clk or posedge i_rst)
if(i_rst)
asy_rst_reg <= 8'd0;
else
asy_rst_reg <= {asy_rst_reg[6:0],asy_rst_wire};
assign asy_rst = asy_rst_reg[7];
/////////////////// spi input ///////////////////
//spi frame 32bit
// wen addr data
// [31] [30:16] [15:0]
always@(posedge clk or posedge asy_rst)
if(asy_rst)
begin
spi_sclk_reg <= 8'd0;
spi_miso_reg <= 8'd0;
spi_nss_reg <= 8'd0;
end
else
begin
spi_sclk_reg <= {spi_sclk_reg[6:0],i_spi_sclk};
spi_miso_reg <= {spi_miso_reg[6:0],i_spi_miso};
spi_nss_reg <= {spi_nss_reg[6:0],i_spi_nss};
end
//get sclk posedge
assign spi_sclk_pos = ~spi_sclk_reg[7] & spi_sclk_reg[6] ;
//get nss negedge & posedge
assign spi_nss_neg = spi_nss_reg[6] & ~spi_nss_reg[5] ;
assign spi_nss_pos = ~spi_nss_reg[6] & spi_nss_reg[5] ;
always@(posedge clk or posedge asy_rst)
if(asy_rst)
spi_cnt <= 8'd0;
else if(spi_nss_neg)
spi_cnt <= 8'd0;
else if(spi_sclk_pos)
spi_cnt <= spi_cnt + 1'b1;
else
spi_cnt <= spi_cnt;
always@(posedge clk or posedge asy_rst)
if(asy_rst)
spi_miso_data <= 32'd0;
else if(spi_nss_neg)
spi_miso_data <= 32'd0;
else if(spi_sclk_pos)
spi_miso_data <= {spi_miso_data[30:0],spi_miso_reg[6]};
else
spi_miso_data <= spi_miso_data;
always@(posedge clk or posedge asy_rst)
if(asy_rst)
begin
spi_addr <= 15'd0;
spi_data <= 16'd0;
end
else
if(spi_cnt == 8'd32)
begin
spi_addr <= spi_miso_data[30:16];
spi_data <= spi_miso_data[15:0];
end
else
begin
spi_addr <= 15'd0;
spi_data <= 16'd0;
end
always@(posedge clk or posedge asy_rst)
if(asy_rst)
spi_cnt_reg <= 16'd0;
else
spi_cnt_reg <= {spi_cnt_reg[7:0],spi_cnt[7:0]};
//address 0-4095 for dds_ram
always@(posedge clk or posedge asy_rst)
if(asy_rst)
spi_wen <= 1'b0;
else if(spi_cnt_reg == {8'd31,8'd32} && spi_miso_data[31:28] == 4'b1000)
spi_wen <= 1'b1;
else
spi_wen <= 1'b0;
//address 4096-16383,16385-32767 reserved
//address 16384 for freq control,low 12bits
reg [15:0]freq_ctrl_reg;
always@(posedge clk or posedge asy_rst)
if(asy_rst)
freq_ctrl_reg <= 16'd0;
else if(spi_cnt_reg == {8'd31,8'd32} && spi_miso_data[31:16] == {1'b1,15'd16384})
freq_ctrl_reg <= spi_miso_data[15:0];
else
freq_ctrl_reg <= freq_ctrl_reg;
////////////////////////dpram////////////////////////
//16*4096
dds_ram u_dds_ram (
.clka ( clk ),
.ena ( 1'b1 ),
.wea ( spi_wen ),
.addra ( spi_addr[11:0] ),//4096-12bit
.dina ( spi_data ),
.douta ( ),
.clkb ( clk ),
.enb ( 1'b1 ),
.web ( 1'b0 ),
.addrb ( phase ),//4096-12bit
.dinb ( 16'd0 ),
.doutb ( o_dac_data )
);
always@(posedge clk or posedge asy_rst)
if(asy_rst)
phase <= 12'd0;
else
phase <= phase + freq_ctrl_reg[11:0];
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst (
.Q(o_dac_clk), // 1-bit DDR output
.C(clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(1'b1), // 1-bit data input (positive edge)
.D2(1'b0), // 1-bit data input (negative edge)
.R(asy_rst), // 1-bit reset
.S(1'b0) // 1-bit set
);
endmodule
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