如下就是特权做的处理，但是对于这个处理我的疑问是：复位信号的第二次处理，即PLL输出后的处理，为什么只用了一个时钟对复位信号的处理，而另外的时钟为什么不处理？是否是只用高频率的时钟处理就行？

module system_ctrl
(
    input       clk,        //50MHz
    input       rst_n,      //global reset
 
    output      sys_rst_n,  //system reset
    output      clk_c0,     
    output      clk_c1,
    output      clk_c2  //-75deg
);
 
//----------------------------------------------
//rst_n synchronism, is controlled by the input clk
reg     rst_nr1,rst_nr2;
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        begin
        rst_nr1 <= 1'b0;
        rst_nr2 <= 1'b0;
        end
    else
        begin
        rst_nr1 <= 1'b1;
        rst_nr2 <= rst_nr1;
        end
end
 
//----------------------------------
//component instantiation for system_delay
wire    delay_done;
system_delay    u_system_delay
(
    .clk        (clk),
    .rst_n      (rst_nr2),
    .delay_done (delay_done)
);
wire    pll_rst = ~rst_nr2 & ~delay_done;   //active High
 
//----------------------------------------------
//Component instantiation
wire    locked; 
sdram_pll   u_sdram_pll
(
    .inclk0 (clk),
    .areset (pll_rst),
    .locked (locked),
             
    .c0     (clk_c0),
    .c1     (clk_c1),
    .c2     (clk_c2)
);
 
//----------------------------------------------
//sys_rst_n synchronism, is control by the highest output clk
   
wire    sysrst_nr0 = rst_nr2 & locked & delay_done;  
reg     sysrst_nr1, sysrst_nr2; 
always @(posedge clk_c1 or negedge sysrst_nr0)
begin
    if(!sysrst_nr0) 
        begin
        sysrst_nr1 <= 1'b0;
        sysrst_nr2 <= 1'b0;
        end       
    else
        begin
        sysrst_nr1 <= 1'b1;
        sysrst_nr2 <= sysrst_nr1;
        end
end
assign sys_rst_n = sysrst_nr2;  //active Low
 
endmodule