LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY latch1 IS
PORT (d:IN STD_LOGIC;
ena:IN STD_LOGIC;
q:OUT STD_LOGIC);
END latch1;
ARCHITECTURE example4 OF latch1 IS
SIGNAL sig_save:STD_LOGIC;
BEGIN
PROCESS (d,ena)
BEGIN
IF ena='1' THEN
Sig_save<=D;
END IF;
Q<=sig_save;
END PROCESS;
END example4;
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