STM32通过FSMC读写CPLD的程序,CPLD挂在STM32的地址线和数据线上,将CPLD看做片外RAM的方式来进行读写,在我做的板子上CPLD挂在第四个区,因此基地址是0x6c000000,通过FSMC来进行读写,程序较为简单,具体的地方在函数中都有注释,仅供参考。
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#include"STM32Lib//stm32f10x.h"
#include"hal.h"
#defineBank1_SRAM4_ADDR((uint32_t)0x6c000000)
voidCPLD_Init(
void)
{
FSMC_NORSRAMInitTypeDefFSMC_NORSRAMInitStructure;
FSMC_NORSRAMTimingInitTypeDefp;
GPIO_InitTypeDefGPIO_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD|RCC_APB2Periph_GPIOG|RCC_APB2Periph_GPIOE|
RCC_APB2Periph_GPIOF,ENABLE);
GPIO_InitStructure.GPIO_Pin=GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_8|GPIO_Pin_9|
GPIO_Pin_10|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode=GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed=GPIO_Speed_50MHz;
GPIO_Init(GPIOD,&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin=GPIO_Pin_7|GPIO_Pin_8|GPIO_Pin_9|GPIO_Pin_10|
GPIO_Pin_11|GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|
GPIO_Pin_15;
GPIO_Init(GPIOE,&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin=GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3|
GPIO_Pin_4|GPIO_Pin_5|GPIO_Pin_12|GPIO_Pin_13|
GPIO_Pin_14|GPIO_Pin_15;
GPIO_Init(GPIOF,&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin=GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3|
GPIO_Pin_4|GPIO_Pin_5;
GPIO_Init(GPIOG,&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin=GPIO_Pin_11|GPIO_Pin_12|GPIO_Pin_13;
GPIO_Init(GPIOD,&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin=GPIO_Pin_4|GPIO_Pin_5;
GPIO_Init(GPIOD,&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin=GPIO_Pin_12;
GPIO_Init(GPIOG,&GPIO_InitStructure);
p.FSMC_AddressSetupTime=0;
p.FSMC_AddressHoldTime=0;
p.FSMC_DataSetupTime=1;
p.FSMC_BusTurnAroundDuration=0;
p.FSMC_CLKDivision=0;
p.FSMC_DataLatency=0;
p.FSMC_AccessMode=FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank=FSMC_Bank1_NORSRAM4;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux=FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType=FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth=FSMC_MemoryDataWidth_8b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode=FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait=FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity=FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode=FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive=FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation=FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal=FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode=FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst=FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct=&p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct=&p;
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4,ENABLE);
}
voidCPLD_Write(uint8_tpBuffer,uint32_tWriteAddr)
{
*(uint32_t*)(Bank1_SRAM4_ADDR+WriteAddr)=pBuffer;
}
uint8_tSRAM_Read(uint32_tReadAddr)
{
uint8_tpBuffer;
pBuffer=*(__IOuint32_t*)(Bank1_SRAM4_ADDR+ReadAddr);
returnpBuffer;
}