---------------------------状态机---------------------------
Library ieee;
Use ieee.std_logic_1164.all;
-------------------------------------------
Entity statem is
Port(clk,clr:in std_logic;
     Q0,Q1,Q2,Q3:out std_logic_vector(6 downto 0));
end;
---------------------------------------------
architecture dd of statem is
Type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal ss0,ss1,ss2,ss3:state;
signal Q:integer range 0 to 19999999;
signal cp:std_logic;
procedure disp(s:in state;p:out std_logic_vector(6 downto 0))is
begin
   case s is
  when s0=>p:="1000000";
  when s1=>p:="1111001";
  when s2=>p:="0100100";
  when s3=>p:="0110000";
  when s4=>p:="0011001";
  when s5=>p:="0010010";
  when s6=>p:="0000010";
  when s7=>p:="1111000";
  when s8=>p:="0000000";
  when s9=>p:="0010000";
  end case;
end disp;
----------1s---------------
begin
process(clk)
   begin
       if clk'event and clk='1' then
            Q<=Q+1;
            if Q=0 then
               cp<=not cp;
            end if;
        end if;
end process;
---------------------------------- 
process(cp)
   begin
   if clr='0' then 
     ss0<=s0;
     ss1<=s0;
     ss2<=s0;
     ss3<=s0;
elsif cp'event and cp='1' then
     case ss0 is
     when s0=>ss0<=s1;
     when s1=>ss0<=s2;
     when s2=>ss0<=s3;
     when s3=>ss0<=s4;
     when s4=>ss0<=s5;
     when s5=>ss0<=s6;
     when s6=>ss0<=s7;
     when s7=>ss0<=s8;
     when s8=>ss0<=s9;
     when s9=>ss0<=s0;
                      case ss1 is
                     when s0=>ss1<=s1;
                     when s1=>ss1<=s2;
                     when s2=>ss1<=s3;
                     when s3=>ss1<=s4;
                     when s4=>ss1<=s5;
                     when s5=>ss1<=s0;
                                      case ss2 is
                                      when s0=>ss2<=s1;
                                      when s1=>ss2<=s2;
                                      when s2=>ss2<=s3;
                                      when s3=>ss2<=s4;
                                      when s4=>ss2<=s5;
                                      when s5=>ss2<=s6;
                                      when s6=>ss2<=s7;
                                      when s7=>ss2<=s8;
                                      when s8=>ss2<=s9;
                                      when s9=>ss2<=s0;
                                                     case ss3 is
                                                     when s0=>ss3<=s1;
                                                     when s1=>ss3<=s2;
                                                     when s2=>ss3<=s3;
                                                     when s3=>ss3<=s4;
                                                     when s4=>ss3<=s5;
                                                     when s5=>ss3<=s0;
                                                     when others=>null;
                                                    end case;
                                     end case;
                    when others=>null;
            end case;
   end case;
end if;
end process;
process(ss0,ss1)
   variable sss0,sss1,sss2,sss3:std_logic_vector(6 downto 0);
   begin
    disp(ss0,sss0);
  disp(ss1,sss1);
  disp(ss2,sss2);
  disp(ss3,sss3);
  Q0<=sss0;Q1<=sss1;Q2<=sss2;Q3<=sss3;
end process;
end;
--------------------------------判断语句-----------------------------------------------------
  Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity statem is
Port(clk,clr:in std_logic;
     Q0,Q1,Q2,Q3:out std_logic_vector(6 downto 0));
end;
architecture dd of statem is
signal ss0,ss2, ss1,ss3:std_logic_vector(3 downto 0);
signal Q:integer range 0 to 12999999;
signal cp:std_logic;
procedure disp0(s0:in std_logic_vector(3 downto 0);p0:out std_logic_vector(6 downto 0))is
begin
   case s0 is
  when "0000"=>p0:="1000000";
  when "0001"=>p0:="1111001";
  when "0010"=>p0:="0100100";
  when "0011"=>p0:="0110000";
  when "0100"=>p0:="0011001";
  when "0101"=>p0:="0010010";
  when "0110"=>p0:="0000010";
  when "0111"=>p0:="1111000";
  when "1000"=>p0:="0000000";
  when "1001"=>p0:="0010000";
  when others=>null;
  end case;
end disp0;
begin
process(clk)
   begin
if clk'event and clk='1' then
      Q<=Q+1;
    if Q=0 then
      cp<=not cp;
   end if;
end if;
end process; 
process(cp)
   begin
     if clr='0' then 
     ss0<="0000";
   ss1<="0000";
   ss2<="0000";
   ss3<="0000";
   elsif cp'event and cp='1' then
    ss0<=ss0+1;
      if ss0=9 then
      ss0<="0000";
      ss1<=ss1+1;
      if ss1=5 then
         ss1<="0000";
       ss2<=ss2+1;
       if ss2=9 then
          ss2<="0000";
        ss3<=ss3+1;
        if ss3=5 then
           ss3<="0000";
       end if;
       end if;
     end if;
    end if;
   end if;
end process;
process(ss0,ss1,ss2,ss3)
   variable sss0,sss1,sss2,sss3:std_logic_vector(6 downto 0);
   begin
    disp0(ss0,sss0);
  disp0(ss1,sss1);
  disp0(ss2,sss2);
  disp0(ss3,sss3);
  Q0<=sss0;Q1<=sss1;Q2<=sss2;Q3<=sss3;
end process;
end;