PIC24F16KL402开发板使用笔记四: Timer1计时器例程

配置Timer1 的操作:
1. 将TON 位置1 (= 1)。
2. 使用TCKPS<1:0> 位选择定时器预分频比。
3. 使用TCS 和TGATE 位设置时钟和门控模式。
4. 将TSYNC位置1或清零来配置同步或异步操作。
5. 将定时器的周期值装入PR1 寄存器。
6. 如果需要中断,将中断允许位T1IE 置1。使用中
断优先级位T1IP<2:0> 来设置中断优先级。

timer1的代码:

  1. /*
  2. * File:   ??mainXC16.c
  3. * Author: Administrator
  4. *
  5. * Created on 2015?3?23?, ??10:20
  6. */
  7. #include "xc.h"
  8. _FBS
  9. (
  10.     BWRP_OFF &      // Boot Segment Write Protect (Disabled)
  11.     BSS_OFF         // Boot segment Protect (No boot flash segment)
  12. )
  13. //_FGS
  14. //(
  15. //    GWRP_OFF &      // General Segment Flash Write Protect (General segment may be written)
  16. //    GSS0_OFF        // General Segment Code Protect (No Protection)
  17. //)
  18. _FOSCSEL
  19. (
  20.     FNOSC_FRC &  // Oscillator Select (8MHz FRC with Postscaler (FRCDIV))
  21.   //  SOSCSRC_ANA &   // SOSC Source Type (Analog Mode for use with crystal)
  22.   //  LPRCSEL_HP &    // LPRC Power and Accuracy (High Power/High Accuracy)
  23.     IESO_ON         // Internal External Switch Over bit (Internal External Switchover mode enabled (Two-speed Start-up enabled))
  24. )
  25. _FOSC
  26. (
  27.    // POSCMD_HS &   // Primary Oscillator Mode (Primary oscillator disabled)
  28.     OSCIOFNC_ON &   // CLKO Enable Configuration bit (CLKO output signal enabled)
  29.     POSCFREQ_MS &   // Primary Oscillator Frequency Range Configuration bits (Primary oscillator/external clock frequency between 100kHz to 8MHz)
  30.     SOSCSEL_SOSCHP &// SOSC Power Selection Configuration bits (Secondary Oscillator configured for high-power operation)
  31.     FCKSM_CSECME    // Clock Switching and Monitor Selection (Clock Switching and Fail-safe Clock Monitor Enabled)
  32. )
  33. _FWDT
  34. (
  35.     WDTPS_PS32768 & // Watchdog Timer Postscale Select bits (1:32768)
  36.     FWPSA_PR128 &   // WDT Prescaler bit (WDT prescaler ratio of 1:128)
  37.     FWDTEN_OFF &    // Watchdog Timer Enable bits (WDT disabled in hardware; SWDTEN bit disabled)
  38.     WINDIS_OFF      // Windowed Watchdog Timer Disable bit (Standard WDT selected (windowed WDT disabled))
  39. )
  40. // Warning:
  41. // Always enable MCLRE_ON config bit setting so that the MCLR pin function will
  42. // work for low-voltage In-Circuit Serial Programming (ICSP). The Microstick
  43. // programming circuitry only supports low-voltage ICSP. If you disable MCLR pin
  44. // functionality, a high-voltage ICSP tool will be required to re-program the
  45. // part in the future.
  46. _FPOR
  47. (
  48.     BOREN_BOR3 &    // Brown-out Reset Enable bits (Enabled in hardware; SBOREN bit disabled)
  49.     PWRTEN_ON &     // Power-up Timer Enable (PWRT enabled)
  50.     I2C1SEL_PRI &   // Alternate I2C1 Pin Mapping bit (Default SCL1/SDA1 Pins for I2C1)
  51.     BORV_V18 &      // Brown-out Reset Voltage bits (Brown-out Reset at 1.8V)
  52.     MCLRE_ON        // MCLR Pin Enable bit (RA5 input disabled; MCLR enabled)
  53. )
  54. _FICD
  55. (
  56.     ICS_PGx3        // ICD Pin Placement Select (EMUC/EMUD share PGC3/PGD3)
  57. )
  58. int main(void) {
  59.     TRISAbits.TRISA0 = 0;
  60.     LATAbits.LATA0 = 1;
  61.     
  62.     //Init timer1.
  63.     T1CON = 0x00;      //Stops the Timer1 and reset control reg.
  64.     T1CONbits.TCKPS0 =1;
  65.     T1CONbits.TCKPS1 =0;
  66.     
  67.     TMR1 = 0x00;       //Clear contents of the timer register
  68.     PR1 = 0x000f;      //Load the Period register with the value 0xFFFF
  69.     IPC0bits.T1IP = 0x01; //Setup Timer1 interrupt for desired priority level.
  70.     
  71.     IFS0bits.T1IF = 0;
  72.     IEC0bits.T1IE = 1;
  73.     T1CONbits.TON = 1;
  74.     
  75.     
  76.     while(1)
  77.     {
  78.         
  79.         ;
  80.     }
  81.     
  82.     return 0;
  83. }
  84. void __attribute__((interrupt, shadow, no_auto_psv)) _T1Interrupt(void)
  85. {
  86.     LATAbits.LATA0 ^= 1;
  87.     /* Interrupt Service Routine code goes here.   */
  88.     IFS0bits.T1IF = 0; //Reset Timer1 interrupt flag and Return from ISR
  89.     
  90. }
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