# Reading D:/altera/13.0/modelsim_ase/tcl/vsim/pref.tcl

# ERROR: No extended dataflow license exists

# do ceshi_run_msim_rtl_verilog.do

# if {[file exists rtl_work]} {

#vdel -lib rtl_work -all

# }

# vlib rtl_work

# vmap work rtl_work

# Copying D:\altera\13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini

# Modifying modelsim.ini

# ** Warning: Copied D:\altera\13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.

# Updated modelsim.ini.

#

# vlog -vlog01compat -work work +incdir+I:/Users/zhao/Desktop/1/4b5b_again_fa {I:/Users/zhao/Desktop/1/4b5b_again_fa/p_8.v}

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module p_8

#

# Top level modules:

#p_8

# vlog -vlog01compat -work work +incdir+I:/Users/zhao/Desktop/1/4b5b_again_fa {I:/Users/zhao/Desktop/1/4b5b_again_fa/fenpin.v}

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module fenpin

#

# Top level modules:

#fenpin

# vlog -vlog01compat -work work +incdir+I:/Users/zhao/Desktop/1/4b5b_again_fa {I:/Users/zhao/Desktop/1/4b5b_again_fa/nrzi_bianma.v}

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module nrzi_bianma

#

# Top level modules:

#nrzi_bianma

# vlog -vlog01compat -work work +incdir+I:/Users/zhao/Desktop/1/4b5b_again_fa {I:/Users/zhao/Desktop/1/4b5b_again_fa/byte_4b5b_bianma.v}

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module byte_4b5b_bianma

#

# Top level modules:

#byte_4b5b_bianma

# vlog -vlog01compat -work work +incdir+I:/Users/zhao/Desktop/1/4b5b_again_fa {I:/Users/zhao/Desktop/1/4b5b_again_fa/ceshi.v}

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module ceshi

#

# Top level modules:

#ceshi

#

# vlog -vlog01compat -work work +incdir+I:/Users/zhao/Desktop/1/4b5b_again_fa/simulation/modelsim {I:/Users/zhao/Desktop/1/4b5b_again_fa/simulation/modelsim/ceshi.vt}

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module ceshi_vlg_tst

#

# Top level modules:

#ceshi_vlg_tst

#

# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneii_ver -L rtl_work -L work -voptargs="+acc" ceshi_vlg_tst

# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneii_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps ceshi_vlg_tst

# Loading work.ceshi_vlg_tst

# Loading work.ceshi

# Loading work.p_8

# Loading work.fenpin

# Loading work.byte_4b5b_bianma

# Loading work.nrzi_bianma

# ** Error: (vsim-3389) I:/Users/zhao/Desktop/1/4b5b_again_fa/simulation/modelsim/ceshi.vt(50): Port 'clk_da' not found in the connected module (3rd connection).

#

# Region: /ceshi_vlg_tst/i1

# ** Error: (vsim-3389) I:/Users/zhao/Desktop/1/4b5b_again_fa/simulation/modelsim/ceshi.vt(50): Port 'data_byte_out' not found in the connected module (5th connection).

#

# Region: /ceshi_vlg_tst/i1

# ** Error: (vsim-3389) I:/Users/zhao/Desktop/1/4b5b_again_fa/simulation/modelsim/ceshi.vt(50): Port 'line1' not found in the connected module (6th connection).

#

# Region: /ceshi_vlg_tst/i1

# ** Fatal: (vsim-3365) I:/Users/zhao/Desktop/1/4b5b_again_fa/simulation/modelsim/ceshi.vt(50): Too many port connections. Expected 4, found 6.

# Time: 0 ps Iteration: 0 Instance: /ceshi_vlg_tst/i1 File: I:/Users/zhao/Desktop/1/4b5b_again_fa/ceshi.v

# FATAL ERROR while loading design

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./ceshi_run_msim_rtl_verilog.do PAUSED at line 16

此错误并不是因为 前边提到的

# ERROR: No extended dataflow license exists

或者最后提示

FATAL ERROR while loading design

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./ceshi_run_msim_rtl_verilog.do PAUSED at line 16

Modelsim_Altera_SE 是FREE的。

此错误原因是因为 编写的testbench 错误；

testbench中：

ceshi i1 (

// port map - connection between master ports and signals/registers

.clk(clk),

.clk_ad(clk_ad),

.clk_da(clk_da),

.data_byte_in(data_byte_in),

.data_byte_out(data_byte_out),

.line1(line1)

);

和 verilog 文件

module ceshi(clk,

data_byte_in,

clk_ad,

led_data_out);

参数不同。导致无法生成仿真波形。