Library Ieee;

Use Ieee.Std_logic_1164.All;

Use Ieee.Std_logic_unsigned.All;

Entity Abc Is

Port(Clk:in Std_logic;

Dout:out Std_logic);

End Abc;

Architecture X Of Abc Is

Signal P,Q:std_logic_vector(2 Downto 0);

Begin

Process(Clk)

Begin

If (Clk''Event And Clk=''1'') Then

If P="100" Then P<="000";Else P<=P+1;

End If;End If;End Process;

Process(Clk)

Begin

If (Clk''Event And Clk=''0'') Then

If Q="100" Then Q<="000";Else Q<=Q+1;

End If;End If;End Process;

Dout<=''1'' When P="000" Or Q="010" Else ''0'';End X;

在MAXPLUS2里编译通过

仿真图也是正确的

这个是2.5分频，如果是其他半整数分频修改参数即可