下面以循环格雷码为例，给出一个VHDL程序。

Library Ieee;

Use Ieee.Std_logic_1164.All;

Entity Demo Is Port(

Clock :In Std_logic;

Q ： Out Std_logic_vector(3 Downto 0)); --Vector的长度随用户而定，这里只是一个示例。

End Demo;

Architecture MyFavor Of Demo Is

Function NxG(Argv :Std_logic_vector) Return Std_logic_vector Is --此函数完成输入一个格雷码返回下一个数的格雷码

Alias GV :Std_logic_vector(1 To Argv''Length) Is Argv;

Variable BV,GC :Std_logic_vector(1 To Argv''Length);

Begin

BV(1) := GV(1);

For I In 2 To Argv''Length Loop

BV(I) := GV(I) Xor BV(I - 1);

End Loop;

GC := GV;

For I In Argv''Length Downto 1 Loop

If BV(I) = ''0'' Or I = 1 Then

GC(I) := Not GC(I);

Exit;

End If;

End Loop;

Return GC;

End NxG;

Signal GC :Std_logic_vector(3 Downto 0);

Begin

Process(Clock) Begin

If Rising_edge(Clock) Then

GC <= NxG(GC);

End If;

End Process;

Q <= GC;

End MyFavor;