代码进行RTL功能仿真
时间:04-14 09:20 阅读:1280次
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简介:调用ModelSim-Altera 功能仿真对代码进行RTL功能仿真
1.建立测试脚本
![](/Uploads/2014_04/article/b86b6ac7f8.jpg)
2.打开工程所文件夹下的simulation文件/.vt文件
3.编辑脚本
![](/Uploads/2014_04/article/0e2d44ca5f.jpg)
4.在setting窗口中做一些设置
![](http://www.61ic.com/FPGA/UploadFiles_9403/201209/20120910110924988.jpg)
![](file:///C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/msohtml1/01/clip_image012.png)
![](/Uploads/2014_04/article/006b1a54ca.jpg)
![](/Uploads/2014_04/article/b91fbce0d3.jpg)
![](/Uploads/2014_04/article/d37f97967f.jpg)
5.Test bench name是.vt文件的文件名;
6.Top level module in test bench是脚本文件中的:
![](/Uploads/2014_04/article/f28b51d9df.jpg)
7.Design instance name in test bench是脚本文件中的:
![](/Uploads/2014_04/article/4a2f8d452d.jpg)
8.添加脚本文件:
![](/Uploads/2014_04/article/ae0cfb2ed1.jpg)
![](/Uploads/2014_04/article/881b68d3a9.jpg)
![](/Uploads/2014_04/article/fb7dcf4d7f.jpg)
![](/Uploads/2014_04/article/07a4e2d07b.jpg)
9.一路确定后
![](/Uploads/2014_04/article/6abe25bbc1.jpg)
10.ok
![](/Uploads/2014_04/article/28006041c4.jpg)