1、Use verilog hdl to implement a flip-flop with synchronous RESET and SET, a Flip-flop with asynchronous RESET and SET.

2、Use verilog hdl to implement a latch with asynchronous RESET and SET.

3、Use Verilog hdl to implement a 2-to-1multiplexer.

4、Use AND gate, OR gate and Inverter toimplement a 2-to-1 multiplexer.

5、Use a 2-to-1 multiplexer to implement a two input OR gate.

6、Use a tri-state buffer to implement Open-Drain buffer.

7、To pide one input clock by3, Written by verilog hdl.

8、To pide one input clock by3, 50% dutycycle is required. Written by verilog hdl.