/****************************Copyright**********************************
**CrazyBird
**http://blog.chinaaet.com/crazybird
**
**------------------------FileInfomation-------------------------------
**FileName:name_interface.v
**Author:CrazyBird
**Data:2015-11-10
**Version:v1.0
**Description:AXI_LITEInterface
**
***********************************************************************/
//synopsystranslate_off
`timescale1ns/1ps
//synopsystranslate_on
modulename_interface
#(
//parameterdefinition
parameterC_S_AXI_ADDR_WIDTH=32,
parameterC_S_AXI_DATA_WIDTH=32,
parameterC_BASEADDR=32'hffff_ffff,
parameterC_HIGHADDR=32'h0000_0000
)(
//globalsignals
inputS_AXI_ACLK,
inputS_AXI_ARESET,
//slaveinterfacewriteaddressports
input[C_S_AXI_ADDR_WIDTH-1:0]S_AXI_AWADDR,
inputS_AXI_AWVALID,
outputS_AXI_AWREADY,
//slaveinterfacewritedataports
input[C_S_AXI_DATA_WIDTH-1:0]S_AXI_WDATA,
input[C_S_AXI_DATA_WIDTH/8-1:0]S_AXI_WSTRB,
inputS_AXI_WVALID,
outputS_AXI_WREADY,
//slaveinterfacewriteresponseports
output[1:0]S_AXI_BRESP,
outputregS_AXI_BVALID,
inputS_AXI_BREADY,
//slaveinterfacereadaddressports
input[C_S_AXI_ADDR_WIDTH-1:0]S_AXI_ARADDR,
inputS_AXI_ARVALID,
outputS_AXI_ARREADY,
//slaveinterfacereaddataports
outputreg[C_S_AXI_DATA_WIDTH-1:0]S_AXI_RDATA,
output[1:0]S_AXI_RRESP,
outputregS_AXI_RVALID,
inputS_AXI_RREADY,
//userports
output[7:0]led_data
);
//------------------------------------------------------
//registervariabledefinition
reg[7:0]reg0;

//------------------------------------------------------
//writeoperation(Don'tchange)
assignS_AXI_AWREADY=S_AXI_AWVALID&S_AXI_WVALID;
assignS_AXI_WREADY=S_AXI_AWVALID&S_AXI_WVALID;
always@(posedgeS_AXI_ACLKorposedgeS_AXI_ARESET)
begin
if(S_AXI_ARESET==1'b1)
S_AXI_BVALID<=1'b0;
elseif((S_AXI_AWVALID&S_AXI_WVALID)==1'b1)
S_AXI_BVALID<=1'b1;
elseif(S_AXI_BREADY==1'b1)
S_AXI_BVALID<=1'b0;
end
assignS_AXI_BRESP=2'b00;

//------------------------------------------------------
//writeoperation(Modifiedbytheuser)
always@(posedgeS_AXI_ACLKorposedgeS_AXI_ARESET)
begin
if(S_AXI_ARESET==1'b1)
begin
reg0<=8'b0;
end
elseif((S_AXI_AWVALID&S_AXI_WVALID)==1'b1)
begin
case(S_AXI_AWADDR[2])
1'b0:reg0<=S_AXI_WDATA[7:0];
default:;
endcase
end
end

//------------------------------------------------------
//readoperation(Don'tchange)
assignS_AXI_ARREADY=1'b1;
always@(posedgeS_AXI_ACLKorposedgeS_AXI_ARESET)
begin
if(S_AXI_ARESET==1'b1)
S_AXI_RVALID<=1'b0;
elseif((S_AXI_ARREADY&S_AXI_ARVALID)==1'b1)
S_AXI_RVALID<=1'b1;
elseif(S_AXI_RREADY==1'b1)
S_AXI_RVALID<=1'b0;
end
assignS_AXI_RRESP=2'b00;

//------------------------------------------------------
//readoperation(Modifiedbytheuser)
always@(posedgeS_AXI_ACLKorposedgeS_AXI_ARESET)
begin
if(S_AXI_ARESET==1'b1)
begin
S_AXI_RDATA<={(C_S_AXI_DATA_WIDTH){1'b0}};
end
elseif((S_AXI_AWVALID&S_AXI_WVALID)==1'b1)
begin
case(S_AXI_ARADDR[2])
1'b0:S_AXI_RDATA<={24'b0,reg0};
default:S_AXI_RDATA<={(C_S_AXI_DATA_WIDTH){1'b0}};
endcase
end
end

//------------------------------------------------------
//userlogic
assignled_data=reg0;

endmodule
//****************************EndFile**********************************