module pwm(
  clk,      //时钟
  reset_n,   //低电平复位
  period,     //周期 
  pulse_width,  //高电平脉冲宽度
  out         //pwm输出
  );
input   clk;
input   reset_n;
input   [15:0]period;    
input   [15:0]pulse_width;
output  out;
reg   [15:0]cnt;  //16位计数寄存器
reg   wave;           //脉冲寄存器
wire  out = wave;    //pwm输出
always @(posedge clk or negedge reset_n)
if(!reset_n)
  cnt <= 0;
else if(cnt<period-1)   //周期可调
  cnt <= cnt + 1;
else 
  cnt <= 0;
always @(posedge clk or negedge reset_n)
if(!reset_n) 
             //占空比可调
wave <= 0;
  else if(cnt<pulse_width)
  wave <= 1;
else 
  wave <= 0;
endmodule