先放我们的实验要求。实验要求不一样的话，慎重参考。
源程序：
//总模块
module FrequencyCounter(
input [1:0] testmode ,
input sysclk ,
input modecontrol,
output highfreq,
output [6:0] hex0,
output[6:0] hex1,
output[6:0] hex2,
output[6:0] hex3
);
wire sigin11;
assign highfreq=modecontrol;
signalinput signalin(.testmode(testmode),.sysclk(sysclk),.sigin1(sigin11));
Frequency freq(.sigin11(sigin11),.sysclk(sysclk),.modecontrol(modecontrol),.hex0(hex0),.hex1(hex1),.hex2(hex2),.hex3(hex3));
endmodule
//频率计模块
module Frequency(sigin11,sysclk,modecontrol,hex0,hex1,hex2,hex3);
input sigin11,sysclk,modecontrol;
// output highfreq;
output [6:0]hex0,hex1,hex2,hex3;
wire [15:0]countBCD;
wire [15:0]locker;
wire OneClk;
wire enable,reset,lock,sigin12;
//signalinput siginai(.testmode(testmode),.sysclk(sysclk),.sigin1(sigin11));
OneHzClk onehz(.sysclk(sysclk),.OneClk(OneClk));
ControlSig controls(.OneClk(OneClk),.enable(enable),.reset(reset),.lock(lock));
TenDivideFre tenp(.sigin(sigin11),.sigin1(sigin12));
TenCounter tencou(.sigin(sigin11),.sigin1(sigin12),.modecontrol(modecontrol),.enable(enable),.reset(reset),.countBCD(countBCD));
lockMachine lockma(.lock(lock),.countBCD(countBCD),.locker(locker));
ShuMa shum(.locker(locker),.hex0(hex0),.hex1(hex1),.hex2(hex2),.hex3(hex3));
endmodule
//siginal Input Module
module signalinput(
input [1:0] testmode,//00,01,10,11????4???????3125?250?50?12500Hz???SW1~SW0???
input sysclk,//????50M
output sigin1//??????
);
reg[20:0] state;
reg[20:0] pide;
reg sigin;
assign sigin1=sigin;
initial
begin
sigin=0;
state=21'b000000000000000000000;
pide=21'b0000000_1111_1010_000000;
end
always@(testmode) begin
case(testmode[1:0])
2'b00:pide=21'b0000000_1111_1010_000000; //3125Hz
2'b01:pide=21'b00000000_1111_1010_00000; //6250Hz
2'b10:pide=21'b01111_0100_0010_0100_0000;//50Hz
2'b11:pide=21'b00000_0000_1111_1010_0000; //12500Hz
endcase
end
always@(posedge sysclk)//?pide??
begin
if(state==0)
sigin=~sigin;
state=state+21'b0_00__0000_0000_0000_0000_10;
if(state==pide)
state=27'b000_0000_0000_0000_0000_0000_0000;
end
endmodule
//1Hz clock module
module OneHzClk(sysclk,OneClk);
reg[25:0] state;
reg[25:0] pide;
input sysclk;
output OneClk;
reg sigin;
assign OneClk=sigin;
initial
begin
sigin=0;
state=26'b00_0000_0000_0000_0000_0000;
pide=26'b10_1111_1010_1111_0000_1000_0000;
//pide=21'b000000_0000_0000_0001000;
end
always@(posedge sysclk)//?pide??
begin
if(state==0)
sigin=~sigin;
state=state+26'b0000_0000__0000_0000_0000_0000_10;
if(state==pide)
state=26'b00_0000_0000_0000_0000_0000_0000;
end
endmodule
//1Hz clk produce control siginal
module ControlSig(OneClk,enable,reset,lock);
input wire OneClk;
output reg enable,reset,lock;
reg countcc;
initial begin
enable=0;
reset=1;
lock=0;
countcc=0;
end
always@(posedge OneClk)
begin
countcc=countcc+1;
if(countcc==0)
begin
lock=0;
reset=1;
enable=1;
end
else if(countcc==1)
begin
lock=1;
reset=0;
enable=0;
end
end
endmodule
//10 counter module
module TenCounter(sigin,sigin1,modecontrol,enable,reset,countBCD);
input wire sigin,sigin1,modecontrol,enable,reset;
output [15:0] countBCD;
wire sigi;
assign sigi=modecontrol?sigin1:sigin;
reg [3:0]count0,count1,count2,count3;
assign countBCD[3:0]=count0;
assign countBCD[7:4]=count1;
assign countBCD[11:8]=count2;
assign countBCD[15:12]=count3;
initial begin
count0=4'b0000;
count1=4'b0000;
count2=4'b0000;
count3=4'b0000;
end
always@(posedge sigi or negedge reset)
begin
if(!reset)
begin
count0=4'b0000;
count1=4'b0000;
count2=4'b0000;
count3=4'b0000;
end
else
begin
if(enable)
begin
count0=count0+4'b0001;
if(count0==4'b1010)
begin
count1=count1+1;
count0=0;
end
if(count1==4'b1010)
begin
count2=count2+1;
count1=0;
end
if(count2==4'b1010)
begin
count3=count3+1;
count0=0;
end
end
end
end
endmodule
//shiliu wei suocunqi mokuai
module lockMachine(lock,countBCD,locker);
input lock;
input wire [15:0]countBCD;
output reg [15:0]locker;
always@(*)
begin
if(!lock)
locker[15:0]=countBCD[15:0];
end
endmodule
//shumaguan mokuai
module ShuMa(input [15:0]locker,output[6:0] hex0,hex1,hex2,hex3);
SevenYimaqi seven0(.A(locker[3:0]),.D0(hex0[0]),.D1(hex0[1]),.D2(hex0[2]),.D3(hex0[3]),.D4(hex0[4]),.D5(hex0[5]),.D6(hex0[6]));
SevenYimaqi seven1(.A(locker[7:4]),.D0(hex1[0]),.D1(hex1[1]),.D2(hex1[2]),.D3(hex1[3]),.D4(hex1[4]),.D5(hex1[5]),.D6(hex1[6]));
SevenYimaqi seven2(.A(locker[11:8]),.D0(hex2[0]),.D1(hex2[1]),.D2(hex2[2]),.D3(hex2[3]),.D4(hex2[4]),.D5(hex2[5]),.D6(hex2[6]));
SevenYimaqi seven3(.A(locker[15:12]),.D0(hex3[0]),.D1(hex3[1]),.D2(hex3[2]),.D3(hex3[3]),.D4(hex3[4]),.D5(hex3[5]),.D6(hex3[6]));
endmodule
//qiduan yimaqi mokuai
module SevenYimaqi(input[3:0] A,output D0,D1,D2,D3,D4,D5,D6);
assign D0=!A[3]&&(!A[2])&&(!A[1])&&A[0]||!A[3]&&A[2]&&!A[1]&&!A[0]||A[3]&&A[2]&&!A[1]&&A[0]||A[3]&&!A[2]&&A[1]&&A[0];//1/4/11/13
assign D1=A[3]&&A[2]&&!A[1]&&!A[0]||!A[3]&&A[2]&&!A[1]&&A[0]||A[3]&&A[2]&&A[1]||A[3]&&A[1]&&A[0]||A[2]&&A[1]&&!A[0];//5/6/11/12/14/15
assign D2=!A[3]&&!A[2]&&A[1]&&!A[0]||A[3]&&A[2]&&A[1]||A[3]&&A[2]&&!A[1]&&!A[0];//2/12/14/15
assign D3=!A[3]&&!A[2]&&!A[1]&&A[0]||!A[3]&&A[2]&&!A[1]&&!A[0]||A[3]&&!A[2]&&A[1]&&!A[0]||A[2]&&A[1]&&A[0];//1/4/7/10/15
assign D4=!A[3]&&!A[2]&&A[0]||!A[3]&&A[2]&&!A[1]||!A[3]&&A[2]&&A[0]||A[3]&&!A[2]&&!A[1]&&A[0];//1/3/4/5/7/9
assign D5=!A[3]&&!A[2]&&A[0]||!A[3]&&!A[2]&&A[1]||!A[3]&&A[1]&&A[0]||A[3]&&A[2]&&!A[1]&&A[0];//1/2/3/7/13
assign D6=!A[3]&&!A[2]&&!A[1]||!A[3]&&A[2]&&A[1]&&A[0]||A[3]&&A[2]&&!A[1]&&!A[0];//0/1/7/12
endmodule
//shifenpin mokuai
module TenDivideFre(sigin,sigin1);
input wire sigin;
output reg sigin1;
reg [3:0]count;
reg r;
initial begin
r=1;
sigin1=0;
count=4'b0000;
end
always@(posedge sigin)
begin
if(count==4'b0100)
begin
sigin1=~sigin1;
count=0;
end
else
count=count+1;
end
endmodule
测试文件：
module FrequencyCounterTest;
reg [1:0]testmode;
reg sysclk,modecontrol;
wire highfreq;
wire [6:0]hex0,hex1,hex2,hex3;
initial begin
sysclk=1;
testmode=2'b01;
modecontrol=1;
end
always #10 sysclk=~sysclk;
FrequencyCounter frecounter(.testmode(testmode),
.sysclk(sysclk),
.modecontrol(modecontrol),
.highfreq(highfreq),
.hex0(hex0),
.hex1(hex1),
.hex2(hex2),
.hex3(hex3)
);
endmodule
仿真波形：
我能说，自己傻到一定程度了吗？？
本来早就应该出来结果了，结果鼻子都撞到了，又折返回来了~~
首先，我竟然一直以为1亿（10的8次方）就是1G（10的9次方）！！！！妈蛋，让我50兆写成了5兆，我说结果咋一直是正确结果的10分之1。。。。。
其次，我用的BCD码，但是后来在modelsim仿真波形里却用unsigned格式来看locker中保存的值，我说咋他妈一直是1573这么奇葩的数。。。。是知道人家是625……傻逼不是一两天。。
最后，苦逼地，终于写出来了，过程很艰辛，但是过后心情很舒畅，自信感爆棚啊！！
学弟学妹们，如果不幸看到了这篇文章，仅当参考，哈~毕竟，还是学习还是需要钻研的。
畅学电子
