1、TLC5620的电路图：

2、TCL5620的时序图：

3、TLC5620的驱动代码：

module TLC5620(clk,rst,write_n,wr_data,dac_clk,dac_data,dac_load,dac_ldac);

input clk;

input rst;

input write_n;

input[10:0] wr_data;

output dac_clk;

output dac_data;

output dac_load;

output dac_ldac;

wire dac_done;

reg dac_clk_r;

reg dac_data_r;

reg [5:0] counter;

reg [31:0] DCLK_DIV;

always @(posedge clk)

if(DCLK_DIV < 32'd500)

DCLK_DIV <= DCLK_DIV+1'b1;

else

begin

DCLK_DIV <= 0;

dac_clk_r <= ~dac_clk_r;

end

always @(posedge dac_clk_r or negedge rst)

begin

if(!rst)

counter <= 0;

else

if(counter<='d13)

counter <= counter + 1'b1;

else

counter <= 0;

end

assign dac_load = (counter == 4'd12) ? 1'b0 : 1'b1;

assign dac_clk = (counter > 'd0 && counter < 'd12) ? dac_clk_r : 1'b0;

assign dac_ldac = (counter == 4'd13) ? 1'b0 : 1'b1;

assign dac_done = (counter <= 4'd11) ? 1'b0 : 1'b1;

assign dac_data = dac_data_r;

/*先高位，把11位数据传输给DAC芯片*/

always @(counter[3:0] or wr_data or dac_done or write_n)

begin

if(!dac_done && !write_n)

case(counter[3:0])

4'd1: dac_data_r <= wr_data[10];

4'd2: dac_data_r <= wr_data[9];

4'd3: dac_data_r <= wr_data[8];

4'd4: dac_data_r <= wr_data[7];

4'd5: dac_data_r <= wr_data[6];

4'd6: dac_data_r <= wr_data[5];

4'd7: dac_data_r <= wr_data[4];

4'd8: dac_data_r <= wr_data[3];

4'd9: dac_data_r <= wr_data[2];

4'd10: dac_data_r <= wr_data[1];

4'd11: dac_data_r <= wr_data[0];

default: dac_data_r <= 1'b1;

endcase

else

dac_data_r <= 1'b1;

end

endmodule

4、锯齿波代码：

module hackle(

input clk, //50MHz

input reset,

output write_n,

output [10:0] write_data );

reg[7:0] data;

assign write_data = {1'b0,1'b0,1'b1,data};

assign write_n = 1'b0;

reg clk_p = 1'b0;//1MHz

reg[8:0] cnt;

always @(posedge clk)

begin

if(cnt < 9'd500)

cnt <= cnt + 1'b1;

else

begin

cnt <= 1'b0;

clk_p <= ~clk_p;

end

end

always @(posedge clk_p or negedge reset)

begin

if(!reset) data <= 8'd0;

else data <= data + 1'b1;

end

endmodule

5、三角波代码：

module triangle(

input clk, //50MHz

input reset,

output write_n,

output [10:0] write_data );

reg[7:0] data;

assign write_data = {1'b0,1'b0,1'b1,data};

assign write_n = 1'b0;

reg clk_p = 1'b0;//1MHz

reg[8:0] cnt;

always @(posedge clk)

begin

if(cnt < 9'd500)

cnt <= cnt + 1'b1;

else

begin

cnt <= 1'b0;

clk_p <= ~clk_p;

end

end

reg flag = 1'b0;

always @(posedge clk_p or negedge reset)

begin

if(!reset) data <= 8'd0;

else if(!flag) data <= data + 1'b1;

else data <= data - 1'b1;

end

always @(posedge clk or negedge reset)

begin

if(!reset) flag <= 1'b0;

else if(data== 8'd255) flag <= 1'b1;

else if(data== 8'd0) flag <= 1'b0;

end

endmodule