用for.....loop.....语句
library ieee;
use ieee.std_logic_1164.all;
entity gelei is
port(B: in std_logic_vector(4 downto 0);
D: out std_logic_vector(3 downto 0));
end gelei;
architecture one of gelei is
begin
process(B)
variable temp:std_logic;
begin
for n in 0 to 3 loop
temp:=B(n) xor B(n+1);
D(n)<=temp;
end loop;
end process;
end one;
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